The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 1999

Filed:

Oct. 24, 1997
Applicant:
Inventors:

Steve P Kornachuk, San Jose, CA (US);

Scott T Becker, San Jose, CA (US);

Assignee:

Artisan Components, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365233 ; 365210 ; 365194 ; 365 51 ;
Abstract

A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordline, and the model wordline is driven by a model wordline driver. The self-timing path also includes a model sense amplifier that is coupled to the model core cell through a pair of model bitlines. The model wordline and the pair of model bitlines are each coupled to a plurality of dummy core cells to approximate an RC delay of a worst case core cell of the array of core cells. Further, the model wordline is a folded wordline, such that the model wordline has a termination at a location that is proximate to the model wordline driver.


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