Channel fn program/erase recovery scheme

Abstract

A recovery circuit for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate coupled to a first node at a first program/erase potential, a floating gate, the channel well coupled to a second node at a second program/erase potential having a first conductivity type, and drain and source regions within the channel well having a second conductivity type different from the first. The recovery circuit includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate to the channel well in response to the recovery control signal. The recovery circuit further includes first and second voltage detectors that generate first and second grounding signals when the control gate and channel well voltages reach a first and second switching voltage respectively. The first and second grounding signals are provided to first and second voltage grounding circuits that bias the control gate and the channel well to the first and second recovery potentials respectively in response to the grounding signals. In one embodiment the first and second recovery potentials are connected to a node at ground potential, and in another embodiment the first conductivity type is p-type. In a further embodiment the floating gate memory cell is a triple well transistor, the channel well of which is within an isolation well on the substrate of an integrated circuit.