The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 1999

Filed:

Jul. 10, 1997
Applicant:
Inventor:

Suguru Tabara, Hamamatsu, JP;

Assignee:

Yamaha Corporation, Hamamatsu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438700 ; 438738 ; 438740 ; 438620 ; 438636 ;
Abstract

A method for manufacturing a semiconductor device having a conductive film formed overlying an insulating film overlying the surface of a semiconductor substrate, the conductive film being made, for example, of a material such as polysilicon, WSi.sub.2, Al and Al alloy, and the like. An antireflection film, made of silicon nitride, for example, is formed overlying the surface of the conductive film, the antireflection film reducing light scattering from the conductive film and having a lower etching rate than the etching rate of the conductive film. The antireflection film is patterned to provide a mask for etching the conductive film, and the conductive film is etched using the patterned antireflection film as a mask to form a gate electrode for an MOS transistor, for example. Source and drain regions, for the MOS transistor, for example, are formed in the semiconductor substrate, and an interlayer insulating film is formed overlying the insulating film overlying the semiconductor substrate, the gate electrode and the antireflection film mask remaining on the surface of the gate electrode. The interlayer insulating film is selectively etched to form a deep contact hole, piercing to the semiconductor substrate in the source region, for example, and a shallow contact hole, piercing to the gate electrode. The antirefiection film mask remaining on the surface of the gate electrode retards the etching of the shallow contact hole so that the etchings of the shallow contact hole and of the deep contact hole are completed substantially simultaneously.


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