The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1999
Filed:
Apr. 24, 1998
Shu-Ya Chuang, Hsinchu-Hsien, TW;
United Semiconductor Corp., Hsin-Chu, TW;
Abstract
A method of fabricating a dual cylindrical capacitor in a DRAM. A semiconductor substrate comprising a gate, a source/drain region, field oxide layer, a first oxide layer covering the whole semiconductor substrate, and a poly-via penetrating through the first oxide layer to electrically connect the source/drain region is provided. A first poly-silicon layer is formed on the first oxide layer and the poly-via. A silicon nitride layer is formed and patterned on the first poly-silicon layer and aligned with the poly-via. An oxide spacer is formed on a side wall of the silicon nitride layer, so that a part of the first poly-silicon layer is covered by the oxide spacer. A part of the first poly-silicon layer is removed with the oxide spacer and the silicon nitride layer as a mask until the first oxide layer is exposed. The silicon nitride layer is removed. A poly-silicon spacer is formed around the oxide spacer. The oxide spacer is removed, so that the remaining first poly-silicon layer and the poly-silicon spacer are combined as a bottom electrode. A dielectric layer is formed on a surface of the electrode. A top electrode is formed on the dielectric layer.