The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Jun. 10, 1998
Applicant:
Inventors:

Takashi Inui, Tokyo, JP;

Masahide Matsumoto, Akishima, JP;

Kiyotaka Okuzawa, Tsukuba, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365203 ; 365149 ; 36518911 ;
Abstract

A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.


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