The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 1999

Filed:

Sep. 30, 1996
Applicant:
Inventors:

Derrick Chu Lin, Foster City, CA (US);

Varsha P Tagare, Sunnyvale, CA (US);

Ramamohan Rao Vakkalagadda, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
713300 ; 713322 ; 712204 ; 712211 ; 712216 ; 712217 ; 712219 ; 712233 ;
Abstract

A method of reducing microprocessor peak power by scheduling execution of instructions to multiple execution units. In the prior art, parallel processing of instructions by high-power execution units caused the microprocessor peak power to increase. The method of the present invention attempts to reduce microprocessor peak power by ensuring that two high-power execution units are not executing simultaneously. While a first instruction is being executed by a first execution unit, a first signal is asserted. A second instruction is prevented from being dispatched to a second execution unit while the first signal is asserted. Thus, the second execution unit remains in an idle state while the first execution unit is executing the first instruction.


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