Method of testing memory operations employing self-repair circuitry and

Abstract

A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry. The test suite may then be re-executed, and the device deemed defective if additional errors are found. Rows and columns in the memory array that are prone to failure are thus never enabled. Additionally, the BIST and BISR circuitry provides the ability to verify basic memory functionality and remap failing addresses on each application of power to the device. Test coverage of the memory array is advantageously increased.