The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 1999
Filed:
Apr. 02, 1997
William Harry Nale, Livermore, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A flexible memory mapper for selectively inverting the state of an address line on an address bus includes a selectable inverter element and a control circuit. The selectable inverter element has a control input coupled to an output of the control circuit, an input, and an output. The control input, the input, and the output are capable of being in two logic levels. When the control input is in a first logic level, the input is passed through uninverted to the output of the selectable inverter element. When the control input is in a second logic level, the input is passed through inverted to the output of the selectable inverter element. The control circuit output feeds one of two logic levels to the control input of the selectable inverter element, outputting the second logic level in response to an input address within a selected address range and a user selectable input bit, and otherwise outputting the first logic level.