Programming current limiter for source-side injection eeprom cells

Abstract

A flash memory EEPROM device with a programming current limiting ability operates with six terminals and includes a source-side injection cell and a current limiter in series with the cell at a source region of the cell. During programming, an upper current limit is established for the overall channel current through the cell by controlling the voltage on a serial-gate of the current limiter. A second embodiment of a flash memory EEPROM device is structured with only four operating terminals, and includes a current limiting transistor integrally merged with a source-side injection cell. Merger is accomplished by eliminating the source junction of the injection cell and by combining the select-gate of the injection cell with the serial-gate of the current limiting transistor to create a conjoint select-gate. The unified channel under the conjoint select-gate consists of two channel sub-sections with different threshold adjustment implants and thus different threshold voltages. The first sub-section of this unique channel, adjacent to the injection point of the cell, is doped with a lower threshold adjustment implant dose than that of the second channel sub-section, adjacent to the source of the memory device. The second channel sub-section, or appended channel, in accordance with the second embodiment is fabricated using a dedicated photoresist mask to dope the second sub-section of the select-gate channel with a higher threshold adjustment implant dose than that for the first sub-section.