The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1999

Filed:

Jun. 06, 1997
Applicant:
Inventors:

Fahd Hinedi, Austin, TX (US);

Moises Cases, Austin, TX (US);

Satyajit Dutta, Austin, TX (US);

Robert Heath Dennard, New Rochelle, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 68 ; 326 71 ; 326 81 ;
Abstract

Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.


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