The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1999

Filed:

Feb. 25, 1998
Applicant:
Inventors:

John J Bush, Leander, TX (US);

Jon D Cheek, Round Rock, TX (US);

Mark I Gardner, Cedar Creek, TX (US);

Assignee:

Advanced Micro Devices, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; G01R / ;
U.S. Cl.
CPC ...
257 48 ; 324765 ; 324769 ; 438 11 ; 438 18 ;
Abstract

The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners. Further, lithographic patterning may lead to a reduction in the lengths of the gate conductors and the conductors. The length of each gate conductor extends along the same axis as the length of the conductor nearest to the gate conductor.


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