The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1999

Filed:

Sep. 20, 1996
Applicant:
Inventors:

Noriyuki Shimoji, Kyoto, JP;

Masataka Tsuruta, Kyoto, JP;

Takuya Yonezawa, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438257 ; 438970 ; 438738 ;
Abstract

A polysilicon layer 38 located upward of a local oxidation of silicon (LOCOS) layer 20 is removed partially when selective etching of the polysilicon layer 38 for forming a floating gate FG is carried out by carrying out anisotropic etching. The etching is stopped when only the polysilicon layer 38 is removed. Wet-etching usually carried out at the final phase of the anisotropic etching process is not performed. In this way, the LOCOS layer 20 located underneath the polysilicon layer 38 is not over-etched. As a result, an inter layer 34 is not formed in a shape of eaves on the LOCOS layer 20 when the inter layer 34 is formed. Therefore, the probability of causing stringers underneath the inter layer 34 is remarkably low.


Find Patent Forward Citations

Shimoji, Noriyuki. (1999). Method for manufacturing a semiconductor device (U.S. Patent No. 5985716). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5985716

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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