Programmable logic device producing a complementary bit line signal

Abstract

A programmable logic device includes a plurality of logic elements. Each logic element includes a raw of transistors formed between a bit line and a source line, elements for generating a complement signal to the bit line signal (the elements have an output complement line) and a differential sense amplifier. Each transistor of the row is connected to a different one of the input lines and has a predefined logic state. The complement line is based on the source line whose signal acts opposite to that of the bit line. The differential sense amplifier is connected to the bit line and to the complement line and indicates when the bit line signal crosses the complement line signal. In one embodiment, the source line signal is raised, in another, the bit line signal is lowered, both with offset circuitry. In a further embodiment, a separate row of transistors (implementing the same logic equation) with a different operating voltage level is provided and the source line of the separate row of transistors acts as the complement line. In all embodiments, the operating voltage levels of one or both of the bit line and complement line are adjusted so that any transition of the source line related signal will cross a corresponding transition on the bit line related signal.