The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 1999

Filed:

Sep. 30, 1997
Applicant:
Inventors:

Krishna Seshan, San Jose, CA (US);

Neal R Mielke, Los Altos Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257776 ; 257758 ; 257773 ; 257723 ; 257620 ; 257700 ; 257734 ;
Abstract

The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls.


Find Patent Forward Citations

Seshan, Krishna. (1999). Metal staples to prevent interlayer delamination (U.S. Patent No. 5977639). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5977639

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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