The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 1999
Filed:
Sep. 15, 1997
Applicant:
Inventors:
Assignee:
National Science Council, Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257198 ; 257197 ;
Abstract
The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction.
Liu, Wen-Chau. (1999). Low offset voltage alinas/gainas heterostructure-confinement bipolar (U.S. Patent No. 5977572). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5977572
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile