The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 1999

Filed:

Nov. 26, 1997
Applicant:
Inventors:

Arnold Siegfried Dietrich, Berg, DE;

Erwin Heinrich, Gauting, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B07C / ;
U.S. Cl.
CPC ...
209573 ; 209571 ; 1983453 ;
Abstract

A connector alignment assembly is provided for aligning memory modules in a test position relative to a memory module tester. An automatic feeder receives, stages and then dispenses the electronic memory modules onto a conveyor, one at a time. The conveyor moves the electronic memory modules from the feeder to a test station. A contact plunger is used to push tester contacts against surface contacts of the electronic memory module to electrically connect the electronic memory module to test circuitry. The connector alignment assembly includes two alignment pins which are mounted to the contact plunger, such that when the contact plunger is moved to press the test contacts against the surface contacts, the alignment pins are moved into two alignment holes of the electronic memory module. Entry of the two alignment pins into the alignment holes aligns the electronic memory module with the test contacts, such that the test contacts register with the surface contacts wherein movement of the contact plunger to press the test contacts against corresponding ones of the surface contacts of the electronic memory module electrically connects the electronic memory module to the test circuitry.


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