Method for fabricating reduced contacts using retardation layers

Abstract

A new method of forming a contact opening through multiple layers is described. A first dielectric layer is deposited over semiconductor device structures formed in and on a semiconductor substrate. A patterned conductor layer is formed overlying the first dielectric layer and covered with a second dielectric layer. A retardation layer is deposited overlying the second dielectric layer wherein the retardation layer has a first etch rate. A third dielectric layer is deposited overlying the retardation layer wherein the third dielectric layer has a second etch rate higher than the first etch rate. A mask is formed over the third dielectric layer having an opening of a first size above one of the semiconductor device structures to be electrically contacted. A contact opening is etched through the first, second, and third dielectric layers and the retardation layer not covered by the mask to the structure to be contacted wherein the contact opening through the third dielectric layer is of the first size and wherein the retardation layer is etched at an angle because of the first etch rate slower than the second etch rate and wherein the contact opening through the second and first dielectric layers underlying the angled retardation layer has a second size smaller than the first size thereby completing the formation of a contact opening in the fabrication of an integrated circuit device.