The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 1999
Filed:
Nov. 19, 1996
Ravi Nagaraj, Hillsboro, OR (US);
Gary A Solomon, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Apparatus and method of assisting software emulation of hardware functions in a processor. During a read cycle on an address bus, an address that is within a predetermined address range is stored in a trap register and a Type-of-Cycle bit in the trap register is set to the read state. If an Issue-SMI-on-Next-Access bit in the trap register is set to the on state, a system management interrupt is issued to the processor. During a write cycle, data on the data bus is stored in a data field of the trap register, the address is stored in the address field of the trap register and the Type-of-Cycle bit is set to the write state. A system management interrupt is issued if the Issue-SMI-on-Next-Access bit is set to the on state. Then the Issue-SMI-on-Next-Access bit is set to the off state. The Type-of-Cycle bit of the trap register is set if the system management interrupt is detected at the processor. Data from the processor is placed into the data field of the trap register if the Type-of-Cycle bit is set to the read state. An I/O restart operation of the processor is then invoked. The Type-of-Cycle bit of the trap register is read if the system management interrupt is detected at the processor. Data from the processor is stored into the data field of the trap register if the Type-of-Cycle bit is set to the read state. An I/O restart operation of the processor is then invoked. The contents of the data field of the trap register are placed on the data bus if the Issue-SMI-on-Next-Access bit is set to the off state. Then the Issue-SMI-on-Next-Access bit is set to the on state.