The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 1999

Filed:

Feb. 06, 1998
Applicant:
Inventor:

Yung-Peng Hwang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 56 ; 326 59 ; 326 31 ;
Abstract

A three-level detector is used to detect the state of a level input pertaining to a relatively-high level, a relatively-low level, or floating. The three-level detector comprises a first inverter, a second inverter, a decision logic circuit, a switching circuit, and a latch. The first inverter and the second inverter, whose inputs are connected to the level input, have a relatively-high threshold voltage and a relatively-low threshold voltage, respectively. The decision logic circuit generates a detected signal representing the state of the level input in response to outputs of the first and second inverters. Moreover, the switching circuit is connected between the level input and a reference level. The latch generates one control signal to regulate the state of the switching circuit. When the state of the level input pertains to either the relatively-high level or a relatively-low level, the switching circuit is turned off. The switching circuit is turned on when the state of the level input is floating.


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