High-speed test system for a memory device

Abstract

A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.