The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Dec. 19, 1996
Applicant:
Inventors:
Sheldon Aronowitz, San Jose, CA (US);
Laique Khan, Milpitas, CA (US);
James Kimball, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438217 ; 438174 ; 438194 ; 438199 ; 438232 ; 438289 ; 438291 ;
Abstract
A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a <100> orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.