High speed dynamic differential logic circuit employing capacitance

Abstract

The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.