The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 1999
Filed:
Dec. 27, 1995
Savita Banerjee, Doylestown, PA (US);
Srimat T Chakradhar, North Brunswick, NJ (US);
Rabindra K Roy, Plainsboro, NJ (US);
NEC USA, Inc., Princeton, NJ (US);
Abstract
A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit. The STM offers numerous advantages over prior art methods namely, (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the asynchronous circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM enforces a fundamental mode of operation during test generation. Experimental results on several benchmarks show that the STM method generates high fault coverage tests with no test invalidation.