Built in self repair for drams using on-chip temperature sensing and

Abstract

A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation. The data on the data bus is stored in a memory location indicated by the address on the address bus. The heating element is coupled to the substrate to heat the memory array to a predetermined operating temperature. The memory device may further include a temperature sensor coupled to the substrate and configured to provide a temperature signal indicative of a temperature of the memory array, and a heating control coupled to receive the temperature signal and coupled to responsively regulate power to the heating element.