The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 1999
Filed:
Aug. 13, 1998
Mehul D Shroff, Cupertino, CA (US);
Rajiv Jain, Palo Alto, CA (US);
Andre Stolmeijer, Washougal, WA (US);
Kathryn E Gordon, Los Altos Hills, CA (US);
QuickLogic Corporation, Sunnyvale, CA (US);
Abstract
A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.