The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Nov. 21, 1996
Raymond M Chu, Saratoga, CA (US);
David J Pilling, Los Altos Hills, CA (US);
John R Mick, San Jose, CA (US);
Integrated Device Technology, Inc., Santa Clara, CA (US);
Abstract
A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an initial rising edge of the clock signal, an initial address is loaded into the first stages of the two-stage address registers. In response to the initial rising edge of the clock signal, the initial address is clocked through the second stages of the two-stage address registers, directly to the memory. Subsequent addresses are derived from the initial address by circuitry within the burst address sequencer. These subsequent burst addresses are provided to the first stages of the addresses registers prior to subsequent rising edges of the clock signal and clocked out to the memory in response to these subsequent rising edges of the clock signal. By providing the addresses directly from the second stage of the address registers to the memory, the logic gate delay associated with providing the addresses to the memory in response to the rising edge of the clock signal is minimized.