The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1999
Filed:
Oct. 29, 1996
Janet Olson, Saratoga, CA (US);
James Sproch, Saratoga, CA (US);
Yueqin Danny Lin, Sunnyvale, CA (US);
Ivailo Nedelchev, Santa Clara, CA (US);
Ashutosh S Mauskar, Sunnyvale, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell 'library' within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition. Specifically, library designers are allowed to specify multiple internal power tables for each output with different 'related.sub.-- pins' fields. To take advantage of the path dependent power modeling, library designers can specify multiple power tables in the library cell with different sets of related.sub.-- pins. Path dependent power modeling is important for those cells for which the path of the toggle makes the cell consume more or less power than the otherwise recorded 'average' power rating used in conventional libraries. One example is the set/reset (SR) flip-flop.