The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 1999

Filed:

Sep. 12, 1997
Applicant:
Inventors:

Lawrence R Gero, Billerica, MA (US);

David M Rowell, Billerica, MA (US);

Assignee:

Kokusai BTI Corporation, North Billerica, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C / ;
U.S. Cl.
CPC ...
219390 ; 118725 ;
Abstract

A semiconductor wafer furnace process tube includes one or more gas delivery lines which wind around the circumference of the process tube in a non-product region near one end to preheat the gas in the lines. The winding section begins within the non-product region of the heater and terminates prior to the location of the first wafer within the process tube. From the termination of the winding section, the delivery lines continue axially directly to the opposite end of the tube. The length of the lines within the winding section is preselected to adequately preheat the gas in the lines before the lines pass the wafers. In this manner, the gas is able to absorb energy from the non-product region of the furnace with minimal or no cooling of the wafers in the product region of the furnace. Additionally, the lines are routed to absorb energy equally around the circumference of the process tube and not create a cold side within the tube. Also, the straight runs past the wafers are equally spaced around the circumference of the tube. In this way, any remaining effect of the gas lines on the tube are balanced.


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