The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 1999

Filed:

Aug. 20, 1996
Applicant:
Inventors:

Kenneth Alfred Bird, New Paltz, NY (US);

Myra Muth Boenke, Hopewell Junction, NY (US);

Jason Lee Frankel, Beacon, NY (US);

Sarah Huffsmith Knickerbocker, Hopewell Junction, NY (US);

Ahmed Sayeed Shah, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438107 ; 438108 ; 438111 ; 257685 ; 257700 ; 257723 ;
Abstract

A universal substrate includes an input/output (I/O) layer having a fixed I/O assignment of I/O locations for connection with a printed circuit board or the like. A chip receiving layer is provided for receiving one of at least two different but allied semiconductor chips, wherein each of the at least two different but allied chips include a set of bond pads and have a unique wire-out requirement. A first layer includes a plurality of bond pads and vias, the plurality of bond pads including at least two sets of bond pads, wherein each set is adapted for bond connection with a respective one of the at least two different semiconductor chips when received by said receiving means and further in accordance with a respective wire-out requirement. A second layer, different from the first layer, includes redistribution lines for coupling the plurality of bond pads and vias of the first layer to the I/O locations of the I/O layer in accordance with the wire-out requirements of the at least two different semiconductor chips and the fixed I/O assignment.


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