The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1999
Filed:
Oct. 24, 1997
Takanori Hirota, Tokyo, JP;
Yasushi Hayakawa, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A level conversion circuit as a semiconductor integrated circuit has a first load resistance (R1), a second load resistance (R2), a first NMOS transistor (MN3) and a second NMOS transistor (MN4) connected to them (R1 and R2) in parallel, respectively, that are driven directly by positive CMOS level signals, a first bipolar transistor (Q1), and a second bipolar transistor (Q2). Both emitters of the first and second bipolar transistors (Q1 and Q2) are connected commonly, and a voltage potential that is lower than a voltage potential of a collector of the first bipolar transistor (Q1) by a predetermined voltage potential is supplied into a base of the second bipolar transistor (Q2).