The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 1999
Filed:
Jul. 12, 1996
Dmitry Messerman, Haifa, IL;
Gershon Hochman, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for extracting a reduced resistor network from an integrated circuit polygon layout is disclosed. The polygon layout includes a Manhattan polygon defined by a plurality of boundary lines. The method involves fracturing the Manhattan polygon along first and second division lines which extend from an intersection point at which first and second boundary lines intersect to define a 270 degree angle within the polygon. The first and second division lines extend parallel to the first and second boundary lines respectively and traverse the polygon so as to fracture the polygon into a number of rectangles. Each rectangle is substituted, or modeled, with a star configuration resistor arrangement, so as to construct a full resistor network. The method then enters an iterative sequence in which network reduction opportunities within the full resistor network are identified, and data concerning each network reduction opportunity is stored. The full resistor network is then reduced to a reduced resistor network by performing a series of reduction steps.