Semiconductor memory integrated circuit

Abstract

There is provided a semiconductor memory integrated circuit which is formed through high-density integration of memory cells and sense circuits and which is capable of ensuring stable operations even in conjunction with a further reduction in voltage and a further increase in the operating speed of the circuit. Two-transistor memory cells, each of which includes a pair of access transistors and a memory capacitor, are arranged in a matrix pattern. A bit line is shared between adjacent columns of memory cells, and a sense circuit is also shared between adjacent columns of memory cells. The sense circuit includes a first sense circuit formed from n-channel MOS transistors, and a second sense circuit formed from p-channel MOS transistors. After a potential difference between signals of the pair of bit lines is amplified to a certain extent by means of the first sense circuit, the second sense circuit is activated to amplify the signal potential difference to a much greater extent.