The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 1999
Filed:
Jun. 07, 1996
Iwao Kumasaka, Kanagawa-Ken, JP;
Yuichi Higuchi, Morioka, JP;
Tokyo Electron Limited, Tokyo-to, JP;
Abstract
One lot is a group of wafers-to-be-processed in one wafer carrier, and one lot region for one lot is allocated fixed to a holding region of a wafer boat. A variable lot region mode in which lot regions for 4, for example, lots are allocated to the wafer boat. When a lot number is less than 4, or numbers of sheets of wafers-to-be-processed in the respective lots are less than a prescribed number, the lot regions can be compressed, centered on a number of a set holding groove is prepared. On the other hand, in connection with transfer of monitor wafers, a mode in which monitor wafers are transferred to inter-lot regions, and a mode in which numbers of holding grooves can be designated are prepared. The former mode is selected in product monitor, and the latter mode is selected in apparatus monitor. The fixed lot region mode in which the respective lots correspond to their holding regions irrespective of numbers of sheets of wafers in the carriers, and the variable lot region mode in which wafers-to-be-processed are transferred to both sides of a designated number of holding groove can be selected by switches. The fixed lot region mode includes a first fixed lot region mode in which wafers-to-be-processed are held in the same arrangement as in the respective carriers, and a second fixed lot region in which wafers-to-be-processed are held without a vacant stage therebetween in respective lot regions. According to the present invention, because of the above-described constitutions, a heat treatment apparatus for heat treating a number of semiconductor wafers, for example, a vertical heat treatment apparatus, can have high freedom degree in arranging wafers-to-be-processed in the wafer boat, and the semiconductor wafers can be transferred suitably in accordance with kinds of heat treatments.