Method of fabricating a capacitor electrode structure in integrated

Abstract

A semiconductor fabrication method is provided for fabricating a capacitor electrode structure in an integrated circuit such as a DRAM (dynamic random-access memory) device to serve as a data storage capacitor for the DRAM device. According to this method, a self-aligned process is used to form the bottom electrode of each data storage capacitor of the DRAM device. The first step is to form a first insulating layer over the substrate, which is then selectively removed to form contact windows. Next, a plurality of polysilicon plugs are formed in these contact windows, with the top surfaces thereof being below the top surface of the first insulating layer by a predefined depth. After this, sidewall spacers are formed on the sidewalls of the remaining void portions of the contact windows. After bit lines are formed, another insulating layer is deposited and then selectively removed to form electrode-pattern openings to expose the polysilicon plug that is to be connected to the bottom electrode of the capacitor. Sidewall spacers are then formed on the sidewalls of the electrode-pattern openings. Finally, a conductive layer is formed over the sidewall spacers in each electrode-pattern opening to serve as the bottom electrode of the capacitor.