System and method for reducing the peak load on the processor of a block

Abstract

A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated from the digital to analog clock of the remote transmit modem having a frequency that may be different than the frequency of the analog to digital clock in the local receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for converting the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle. The invention also contemplates a modem transmitter that includes a buffer that receives L samples per block from the digital processor and supplies a block of size L-A samples to a digital to analog converter. The buffer accumulates A samples on each block transfer and when there are L-A samples in the buffer, a block of L-A samples is passed without receiving any additional samples from the digital processor.