Method and apparatus for controlling memory address hold time

Abstract

A self timed memory address control circuit is described. A Y address signal is pre-decoded and then latched. Address transition detection circuits coupled to X and Y address lines output a pulse to an equalization circuit whenever one of the corresponding address signals change. The WEB address detection circuit outputs a pulse when the WEB signal switches high. When the equalization circuit receives one of these pulses it generates an output pulse to an equalization transistor that is coupled between two local I/O bus lines. The equalization circuit output pulse turns on this transistor to equalize the local I/O bus lines so as to prevent data from being written with them. The equalization circuit also outputs a pulse to a clock generator circuit. The clock generator circuit generates a clock signal which clocks the latch. This causes the latch to couple the pre-decoded output signals to a decoder. The decoder then combines the pre-decoded address signals with other control signals. The decoder then activates the appropriate column select lines. Shortly thereafter the equalization pulse switches low, and a write pulse signal switches high to write data into the selected memory cell. This ensures that at the end of a write operation, when the Y address changes and WEB changes from low to high, the column select will change only after the equalization signal is asserted. The equalization pulse remains high to keep the local I/O bus lines equalized until after the write pulse has switched low. This thereby avoids the uncertainty in the matched delay requirements between the equalization signals and the decoded address signals of conventional asynchronous memory devices and prevents data from being improperly written into the memory address for the subsequent cycle.