The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 1999
Filed:
Sep. 17, 1997
Applicant:
Inventors:
Jonathan F Churchill, Reading, GB;
Neil P Raftery, Guildford, GB;
Colin J Hendry, South Maidenhead, GB;
Jeyakumar Shanmugam, San Jose, CA (US);
Mark A Finn, Mountain View, CA (US);
Thomas M Surrette, Saratoga, CA (US);
Cathal G Phelan, Mountain View, CA (US);
Ashish Pancholy, Milpitas, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 2231 ;
Abstract
A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.