Dram transistor cells with a self-aligned storage electrode contact

Abstract

A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions. The channel electrode may include a channel line formed on a channel line insulation layer on the dielectric region and having a channel line extension extending through the channel line insulation layer into the dielectric region, and a channel electrode plug extending from the channel line extension to the second source/drain region. Alternatively, the channel electrode includes a channel line formed overlying the second source/drain region and extending to directly contact the second source/drain region. A channel line cap preferably covers top and sidewall portions of the channel line, and a storage electrode formed along a sidewall portion thereof.