The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 1999

Filed:

Oct. 14, 1997
Applicant:
Inventors:

Chang-Ming Dai, Hsinchu, TW;

Jammy Chin-Ming Huang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F / ;
U.S. Cl.
CPC ...
430312 ; 430314 ; 430316 ; 438724 ;
Abstract

A new method is disclosed for forming dual damascene patterns using a silylation process. A substrate is provided with a tri-layer of insulation formed thereon. A first layer of silylation photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a mask. Using a silylation process, which greatly improves the depth of focus by reducing reflections from the underlying substrate, the regions in the first photoresist adjacent to the hole pattern are affixed to form top surface imaging mask. The hole pattern is then etched in the first photoresist. A second layer of photoresist is formed, and is imaged with a line pattern aligned with the previous hole pattern by exposure through a mask. The line pattern in the second photoresist is etched. The hole pattern in the first photoresist is transferred into the top layer of composite insulation first and then into the middle etch-stop layer by successive etching. The line pattern in the second photoresist layer is transferred into the first photoresist layer through a subsequent resist dry etching process. Finally, the line pattern and the hole pattern are transferred simultaneously into the top and lower layers of the composite insulation layer, respectively, through a final dry oxide etching. Having thus formed the integral hole and line patterns into the insulation layer, metal is deposited into the dual damascene pattern. Any excess metal on the surface of the insulating layer is then removed by any number of ways including chemical-mechanical polishing, thereby planarizing the surface and readying it for the next semiconductor process.


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