System and method for a flexible memory controller

Abstract

A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles. When a read address matches the address of a pending write operation it indicates that the data that the read address is intended to retrieve has not yet been written to the memory array. The data for this read operation may be in one or more places including the memory I/O pins, either of the two data registers, or inside the memory. The state machine includes a series of logical comparisons to identify the location of the desired data. After the data location is determined the data is loaded into the output register.