The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 1999

Filed:

Jun. 09, 1997
Applicant:
Inventors:

Kenji Tsuchida, Kawasaki, JP;

Yukihito Oowaki, Yokohama, JP;

Kazunori Ohuchi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365207 ; 365 51 ; 36523003 ; 365205 ;
Abstract

A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.


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