Method for device ruggedness improvement and on-resistance reduction for

Abstract

The invention discloses method for fabricating a MOSFET on a substrate to improve device ruggedness. The method includes steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and growing an initial oxide layer over the epi-layer; (b) applying an active mask for etching the active layer to define an active area followed by depositing an overlaying polysilicon layer and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the mask and carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the blocking mask and a source diffusion process; (e) forming an overlying insulation layer covering the MOSFET followed by applying a contact mask to open a plurality of contact openings; (f) performing a low energy body-dopant and high energy body dopant implant to form a shallow high-concentration body dopant and a deep high-concentration body dopant region followed by applying a high temperature process for densification of the insulation layer and activating diffusion of the deep and shallow body dopant regions wherein the deep high-concentration body-dopant regions are formed below the source regions and extends beyond the contact regions but are kept at lateral distance away from a channel region of the MOSFET in the body region whereby device ruggedness is improved without increasing threshold voltage.