The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1999
Filed:
Jul. 02, 1997
Patrice Michael Parris, Phoenix, AZ (US);
Yee-Chaung See, Phoenix, AZ (US);
Irenee M Pages, Villeneuve Tolosane, FR;
Juan Buxo, Mesa, AZ (US);
Eric Scott Carman, Toulouse, FR;
Thierry Michel Sicard, Mesa, AZ (US);
Quang Xuan Nguyen, Castanet, FR;
Motorola, Inc., Schaumburg, IL (US);
Abstract
A single level gate NVM device (20) includes a floating gate FET (11) and a capacitor (12) fabricated in two P-wells (27, 28) formed in an N-epitaxial layer (22) on a P-substrate (21). P+ sinkers (29, 31) and N-type buried layers (25, 26) provide isolation between the two P-wells (27, 28). The NVM device (20) is programmed or erased by biasing the FET (11) and the capacitor (12) to move charge carriers onto or away from a conductive layer (36) which serves as a floating gate (14) of the FET (11). Data is read from the NVM device (20) by sensing a current flowing in the FET (11) while applying a reading voltage to the capacitor (12).