The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1999
Filed:
Jun. 19, 1997
Keith Frederick Underwood, El Dorado Hills, CA (US);
Richard Joseph Durante, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The pipeline architecture minimizes delays incurred during execution of branch instructions. While a first instruction is executing, a second instruction is fetched and is ready for execution at the beginning of the next clock cycle. Control logic examines the fetched instruction during the first clock cycle to determine whether the instruction is a branch instruction which may indicate that the address of the next instruction is not the next sequential address. Flags which indicate the state of the system are examined to determine if the address of the instruction is the next sequential address or the address indicated in the branch instruction. As this is performed during the fetch clock cycle of the branch instruction, during execution of the branch instruction, the instruction at the address selected is fetched and is ready for execution without delay.