Shift register functioning in both latch mode and counter mode and flash

Abstract

The shift register includes a front stage latch portion for inputting input data when a clock signal is at a first level and latching the input data when the clock signal is at a second level, a rear stage latch portion for inputting data from the front stage latch portion when the clock signal is at the second level and latching the input data when the clock signal is at the first level, an input switch for connecting a data input terminal to the front stage latch portion when a mode switching signal is at a first level, and a feedback switch for connecting the rear stage latch portion to the front stage latch portion when the mode switching signal is at a second level. A latch mode clock signal is provided as the aforementioned clock signal when the mode switching signal is at the first level, and a counter mode clock signal or front stage shift register latch output signal is provided as the aforementioned clock signal when the mode switching signal is at the second level. The shift register functions in latch mode when the mode switching signal is at the first level, and functions with a plurality of stages thereof as a counter when at the second level. A flash memory equipped with the above shift registers which have a function whereby command flags of decoded external command signals are latched, and a counter function whereby counting is performed with the plural shift register stages.