The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1999
Filed:
Apr. 28, 1997
Gregory Illes, San Jose, CA (US);
Kenneth L Skala, Fremont, CA (US);
Richard B Morris, San Jose, CA (US);
Duane A Champoux, San Jose, CA (US);
Credence Systems Corporation, Fremont, CA (US);
Abstract
An integrated circuit (IC) tester includes a set of nodes providing test access to separate terminals of an IC and each carrying out a sequence of actions at the terminal in response to test vector sequences. Each node includes a low speed vector memory supplying test vectors during the test. A host writes vectors into the vector memories before the test sending them over a common bus to vector write caches within each node. The write caches compensate for access speed limitations of the vector memory. During the test, blocks of vectors are read out of the vector memory at a low rate and written into a high speed read cache array. An instruction processor within each node reads individual vectors read out of the read cache array at a high rate and uses them for controlling test operations at the node during each cycle of the test. The read cache array not only compensates for the low speed vector memory, it also allows the instruction processor to re-use repeated vector patterns, thereby reducing the number of vectors that must be distributed to the nodes.