Semiconductor device and test method and apparatus for semiconductor

Abstract

A semiconductor device having a multi-bit data input/output terminal is tested or inspected by use of a conventional testing apparatus. The semiconductor device is divided into a number of memory cell blocks, and test data comprised of a limited number of bits corresponding to the number of bits of the data I/O terminal of each memory cell block is supplied to each memory cell block. Each memory cell block has a buffer circuit located between adjacent ones of the data buses corresponding to the respective I/O terminals. Each memory cell block also has first to test buffer circuits. The test buffer circuits include an i-th test buffer circuit (i a natural number in the range of) which has one connected to the first data bus and the other end connected to the data bus. The first to n-th buffer circuits and the first to test buffer circuits are switched between active and inactive by controlling timing signals supplied thereto.