The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 1999

Filed:

Jan. 30, 1998
Applicant:
Inventors:

Naoya Okamoto, Kanagawa, JP;

Hitoshi Tanaka, Kanagawa, JP;

Naoki Hara, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257410 ; 257288 ; 257289 ; 257290 ; 257368 ; 257411 ;
Abstract

An undoped GaAs layer and a GaAs active layer are formed on a GaAs semiconductor substrate in that order, and a surface of the GaAs active layer is inactivated. Thereafter, a wafer composed of the GaAs semiconductor substrate, the undoped GaAs layer and the GaAs active layer is annealed at temperatures ranging from 570 to 580.degree. C. in a molecular beam epitaxy apparatus. Thereafter, the wafer is maintained at temperatures ranging from 350 to 500.degree. C., and an insulating layer made of amorphous GaAs is formed on the GaAs active layer while using tertiary-butyl-gallium-sulfide-cubane '((t-Bu)GaS).sub.4 ' as a source of the insulating layer. Thereafter, the insulating layer is patterned according to a photo-lithography method to form a gate insulating layer on the GaAs active layer. Thereafter, a source electrode and a drain electrode are formed on both sides of the gate insulating layer to arrange the source and drain electrodes separated from each other on the GaAs active layer, and a gate electrode is formed on the gate insulating layer.


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