Enhanced power managing unit (pmu) in a multiprocessor chip

Abstract

A power management circuit for use with multiple processors integrated on the same chip where one or more of the processors may run at different clock speeds from the others or be stopped. Clock generation circuitry including a power management unit which provides three power management modes, namely power down mode, idle mode and standby mode, plus separate control of each microprocessor core is utilized. In power down mode, the clocks that drive the general purpose processor core, and the other processors and all peripherals are stopped and the oscillator circuit which provides the clock signals to a circuit used to generate the clock phases used by the processors and peripherals are shut off. In idle mode, only the general purpose microprocessor clock is stopped while the peripherals are running. Standby mode is similar to power down mode in that the clocks that drive the general purpose microprocessor and the other processors and all peripheral clocks are stopped. However, unlike power down mode, during standby mode, the oscillator and the associated clock generation circuitry keep running so the part can wake up quickly. In providing for the separate control of the additional microprocessor cores, in addition to allowing the user to stop the additional cores when they are not needed, the additional cores are stopped when the part comes out of a reset thus preventing the additional cores from executing any program code until after the general purpose microprocessor core has completed its initialization and uploaded application program needed by other cores or processor.