Fabrication process for semiconductor device

Abstract

A Fabrication process for a semiconductor device, in which an element separation region and a gate insulation layer are formed on a surface of a silicon layer of a semiconductor substrate. Then, a gate electrode wiring is formed on the surface of the silicon layer and an insulation layer spacer is formed at the side surface of the gate electrode wiring. Diffusion layers to be a source and drain regions are formed in a predetermined region on the surface of the silicon layer. At least the surface of the diffusion region is converted into an uneven surface. Then, a refractory metal (e.g. titanium layer) is deposited on the entire surface, a refractory metal silicide layer is selectively formed on at least one of the surfaces of the diffusion layers by annealing, and a non-reacted refractory metal layer is selectively removed. Thus, in advance of deposition of titanium layer, unevenness is formed on the exposed surfaces of the diffusion layers and the upper surface of the polycrystalline silicon layer. This allows a MOS transistor of the salicide structure to be formed without increasing sheet resistance even when high temperature annealing is performed.